The present invention relates to integrated circuit structures and fabrication methods, and more particularly to smart power structures which include n-channel lateral DMOS as well as logic transistors.
Background: DMOS and LDMOS
DMOS devices are “double diffused” metal oxide semiconductor (MOS) field effect transistors, or MOSFETs. DMOS are power devices which can be used as individual devices or as components within power integrated circuits. A DMOS is characterized by a source region and a body (or backgate) region which are simultaneously diffused, so that the transistor's channel length is defined by the difference between two diffusion lengths, rather than by separate a patterned dimension. The double-diffusion structure of the DMOS transistor enables a short channel to be formed with high precision. A short channel region provides the ability to control large drain currents by means of the gate voltage. (A drift region separates the short channel from the drain structure, to provide sufficient stand-off voltage capability.) A second advantage is the reduced switching time. That is, DMOS devices have an advantage over other transistor designs through decreasing the length of the channel to provide low-power dissipation and high-speed capability.
DMOS transistors are grouped into vertical DMOS (VDMOS) transistors and lateral DMOS (LDMOS) transistors according to the direction of the current path. An LDMOS has its contacted source and drain regions near at the surface of the semiconductor wafer, and thus, the current traveling across the transistor is more or less lateral in nature.
Background: Secondary Carrier Generation
One of the basic phenomena in power devices is secondary carrier generation: charge carriers can multiply. For example, in an n-channel LDMOS device an electron will often generate additional electron-hole pairs when it enters a region of high electric field (e.g. at the drain boundary). The holes thus created will travel in the opposite direction (since they have opposite charge), and will normally flow back toward the source/channel boundary. The amount of secondary hole current depends on: 1. The magnitude of electric field in the drain depletion layer; and 2. The magnitude of the electron current that is flowing in the channel (the primary current Ich).
Background: Safe Operating Area (SOA)
An important characteristic of LDMOS devices (as of other power transistors) is the “safe operating area” (SOA). The more current a transistor is carrying, the less voltage it can withstand; and the more voltage a transistor must control, the less current it can safely carry. Thus the SOA describes the set of voltage/current values where safe operation is possible. More precisely, if we look at the plot of drain current Id versus drain-source voltage Vds, the SOA describes the range of values within which it is possible to operate the device without damage or destruction. Because temperature plays a role in determining the SOA, the SOA boundary is necessarily a function of pulse duration, with longer pulses having a reduced SOA.
A transistor loaded only by a pure resistance will have only one line of voltage/current values for a given gate voltage, but in real-world applications the operating point can also be affected by the load's reactive and/or hysteretic characteristics. Thus movement within the SOA occurs as the LDMOS interacts with the circuit, and there is a risk that switching transients can lead to current/voltage trajectories that cross the boundary of the SOA. When this boundary is crossed, negative resistance occurs and “snapback” of the current-voltage characteristic can take place, i.e. The transistor may start to conduct very large currents. A transistor in this state is likely to destroy itself or its power supply connections.
Thermal effects are also involved: when a transistor is operating under high current and high bias, heat will be generated. Because physical behavior responsible for initiating snapback is a function of temperature, it is important to keep track of ambient temperature and pulse conditions so that the device junction temperature can be determined. Thus caution is needed in specifying SOA at room temperature, since the worst-case conditions occur when the device is hot.
SOA performance is a particular problem for N-channel Ldmos transistors. Such transistors are generally used as IC output drivers, because the Rsp vs. BVdss tradeoff is more favorable than for a p-channel Ldmos, In addition, circuit topologies tend to favor an n-Ldmos in these and other power applications. However, a drawback of the n-Ldmos is that its safe operating area is generally inferior to that of a p-Ldmos.
Background: Parasitic Bipolar
Many semiconductor devices can operate in more than one way, and the undesired modes of operation are referred to as “parasitic” modes or devices. In an n-channel LDMOS, the n-type source, p-type body (and drift region), and n-type drain define a parasitic NPN bipolar transistor, which plays an important part in limiting the SOA. The negative resistance and snapback behavior are due to the presence of this parasitic bipolar transistor (which is unavoidably present in all LDMOS transistors). The bipolar emitter, base, and collector regions of the parasitic bipolar are equivalent to the source, body (or backgate), and drain regions of the LDMOS. At high currents and high voltages, the parasitic bipolar transistor can be turned on by carriers (holes) created by impact ionization in the drain region of the LDMOS. The typical LDMOS base region has a fairly high sheet resistance, so high currents can create enough base-emitter voltage drop to turn on the parasitic bipolar. Once the parasitic bipolar turns on, continued generation of secondary holes at the drain side will keep the bipolar on until the device is destroyed (or current is otherwise limited).
Some generation of secondary holes occurs under many operating conditions. However, the danger is in uncontrolled current, i.e. in the negative resistance condition mentioned above. When the secondary hole current turns on the parasitic NPN device, this device begins to provide a secondary electron current. If the ratio of secondary electrons per secondary hole times the ratio of secondary holes per electron exceeds one, the secondary electron current and secondary hole current are in a positive feedback relationship, and the device is no longer controlled by the gate.
Impact ionization is the process where a carrier drifting under a high electric field (say an electron at the drain side of an n-LDMOS) generates another pair of carriers. The lower SOA of n-LDMOS (as compared p-LDMOS) is mainly due to the larger value of the impact ionization coefficient of electrons versus holes. If we use critical field Ec as a gauge of the propensity to electrical snapback, the difference in impact ionization coefficients can lead to critical fields of only 1.5e5 V/cm for an n-Ldmos, as opposed to 3e5 V/cm for a p-Ldmos. This factor of two difference in critical field corresponds to a factor of FOUR difference in power density, so it can be seen that the limited SOA of n-channel LDMOS devices is a very significant limitation.
LDMOS with Improved Safe Operating Area
The present application discloses n-type LDMOS devices in which a low resistance shunt path is provided for the holes that are generated in the drain region due to impact ionization. As seen in FIG. 1, a heavily-doped p-type “buried body” region is placed beneath the source and p-type body, preferably using an implantation through the same mask window as the source and body dopants. This buried body region provides a low-impedance path which collects a large fraction of the secondary hole current, so that these holes do not forward bias the base-emitter junction of the parasitic npn bipolar.
This structure has been shown to make the overall propensity to snapback much lower, and with sufficient dosage in the buried body the critical field can be increased to nearly the bulk breakdown value.
The results found with this structure are surprisingly different from those found with high-energy retrograde wells: the results reported with high-energy retrograde wells did not show any major improvement over that for more conventional Ldmos.
The disclosed structure not only collects secondary holes efficiently, but also reduces the base resistance and hence the base-emitter voltage drop. (If the base-emitter voltage drop is less than one diode drop, or approximately one volt, the parasitic bipolar device cannot turn on.)
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:    Higher critical field;    Larger safe operating area for n-channel LDMOS devices;    Reduced susceptibility to voltage transients;    Increased reliability of smart-power devices;    Simple fabrication (no increased mask count);    Increased power handling for a given chip area.